Dustin Forman on the Sabre chip*: "The chip works with a 6-bit noise shaper but register 15 can set the quantizer to 6, 7, 8 or 9 bits. I found that 6-bit mode and running the same data into the inputs and paralleling the outputs, THD+N and DNR were best. The default configuration in 8-channel mode is a pair of 6-bit DACs operating in anti phase making up each channel. The DACs are a Thevenin equivalent to a voltage source so you may choose to connect their outputs to a voltage mode (non-inverting amplifier) configuration or to a virtual-ground current mode (inverting amplifier). The highest THD performance is via the current mode. The default configuration for stereo mode and the only configuration that can use the S/PDIF input is to wire four output channels in parallel. When stereo mode is enabled in the configuration registers, the same data is sent to all four channels. Effectively now the DACs become a pair of 8-bit DACs to typically allow >132dB of DNR. THD in the stereo current mode is limited by the external components and measurement equipment.


"We recommend using an extremely good op-amp for the highest performance I/V conversion but even an excellent op-amp is the limiting factor in THD. The most important thing to get THD in the better-than 116dB region is a nice line-of-sight solid ground plane back to AGND_L /R with as little interruption to these returns from the I/V converter loads. Simply rerouting grounds, we have seen 10dB differences in THD performance. If you care more for best THD, then only have 2Vrms or so on the output of your I/V converters.


"The data path in the Sabre DAC is 24 bits in, 24 bits coeff, 56bit MAC and 28 bits to the modulator. I experimented with 36 bits to the modulator in prototypes but dropped back to 28 since in my design, that's where the digital noise floor dropped out of sight. But there is still some filtering going on at the 28-bit level before the signal hits the noise shaper or even the jitter blocker.


"There is no analog PLL inside the chip. The data simply comes into the chip at the bit-clock rate, then a circuit takes the date into the XI clock domain and makes sure no jitter is introduced... Both the Sabre Reference and Ultra chips have -120dB image rejection in their oversampling filters, the Sabre Premier has 60dB when configured in stereo mode. The impulse response is almost symmetrical due to an FIR and IIR filters in the path. The reason for the 0.005dB pass band ripple figure is that I wanted 120dB image rejection."


To the question of "what factors in a DAC do you consider of greatest importance for subjective sound quality?", Dustin answered: "This is a tough question and many people carry vastly differing opinions on this subject. All I can say is what I used as the methodology when designing the DAC. 1/ most important in this design was immunity to jitter no matter what transport was used; 2/ to keep the response 'linear phase' so group delay was constant; 3/ use enough bits in each part of the chain such that the quantization error was not enough to cause degradation of DNR at final output; 4/ use a simple dynamic element matching algorithm and not making anything more complicated than it needed to be; 5/ (here I spent most the time) doing a darn good job of matching everything, even parasitics in the analog section of the chip."


On the digital volume control implementation: "Volume in this DAC is done just before the data goes into the FIR filter. It is not just a multiply-by-a-scale-factor type volume control. It's a circuit Martin Mallinson first patented, then I added on to in a further patent so he is the one to be credited with the idea. It uses a scheme that forces a logarithmic response from one level to the next. The algorithm uses 28 bits to keep the rounding errors minimized. On top of that, when the volume moves to a new level, it moves in 1/64th dB steps to make sure the 'clicking' of some implementations is inaudible."

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The above was extrapolated from the diyaudio.com Sabre DAC thread